This is what I was able to collect regarding architecture and components. It's all public.
The main X86 (hu-intel) CPU is a Tunnel Creek with 1GB RAM. Most likely: https://www.intel.com/content/www/u...e660t-512k-cache-1-30-ghz/specifications.html
A QNX driver "dev-speedstep" varies the CPU clock from 600-1300 MHz.
The Gateway side is a TI DRA446 (Jacinto). ARMv9 324MHz, 64MB RAM, 64MB flash.
HW <= 08 have an internal Gyroscope (like CIC). HW 21 and 31 do not. This means that for accurate GPS positioning, messages 0x199, 0x19A and 0x19F which would normally be sent by the ICM need to be "emulated.
Units with connector A42*3B above Quadlock have 4 FBAS inputs - 2 in A42*3B, 2 in QuadLock.
The main X86 (hu-intel) CPU is a Tunnel Creek with 1GB RAM. Most likely: https://www.intel.com/content/www/u...e660t-512k-cache-1-30-ghz/specifications.html
A QNX driver "dev-speedstep" varies the CPU clock from 600-1300 MHz.
Total Cores | 1 |
Total Threads | 2 |
Processor Base Frequency | 1.30 GHz |
Cache | 512 KB L2 Cache |
Bus Speed | 2500 MHz |
TDP | 3.6 W |
The Gateway side is a TI DRA446 (Jacinto). ARMv9 324MHz, 64MB RAM, 64MB flash.
HW <= 08 have an internal Gyroscope (like CIC). HW 21 and 31 do not. This means that for accurate GPS positioning, messages 0x199, 0x19A and 0x19F which would normally be sent by the ICM need to be "emulated.
Units with connector A42*3B above Quadlock have 4 FBAS inputs - 2 in A42*3B, 2 in QuadLock.
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